Kaohsiung, Taiwan

Bo-Hong Chen

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Bo-Hong Chen. Retrieved from https://idiyas.com/inventor/bo-hong-chen-lw0rw2sy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Bo-Hong Chen: Semiconductor Invention and Patent

Introduction

Bo-Hong Chen is an inventor associated with Kaohsiung, Taiwan. His work includes a patented semiconductor design developed in connection with Taiwan Semiconductor Manufacturing Company Limited. His patent record includes 1 patent.

Latest Patents

Chen is named on “Isolation Structures for Multi-Gate Devices.” The patent describes a semiconductor structure with two base fins rising from a substrate and an isolation structure between them. Channel members sit above each fin, with gate structures wrapping around the respective channel members. Gate-cut features extend through the gate structures and into the isolation feature, while remaining spaced apart from a region-isolation feature. The design addresses isolation arrangements in multi-gate semiconductor devices.

Career Highlights

Chen’s documented patent work concerns semiconductor device structures and isolation features. The patent is associated with Taiwan Semiconductor Manufacturing Company Limited, a semiconductor company.

Collaborations

Chen’s listed coworkers include Ya-Yi Tsai and Chi Yuen Pak. Their names are provided as collaborators associated with his professional context.

Conclusion

Bo-Hong Chen’s patent on isolation structures for multi-gate devices reflects his contribution to semiconductor design and his association with Taiwan Semiconductor Manufacturing Company Limited.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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