Boise, ID, United States of America

Attila A Herrera

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Micron Technology Incorporated. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Attila A Herrera. Retrieved from https://idiyas.com/inventor/attila-a-herrera

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Attila A Herrera: Innovator in Memory Systems

Introduction

Attila A Herrera is a notable inventor based in Boise, ID (US). He has made significant contributions to the field of memory systems, particularly through his innovative patent that addresses the reliability of memory components.

Latest Patents

Attila holds a patent titled "Dynamic word line allocation in memory systems." This patent focuses on configuring a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of memory components. It determines that one or more WLs are associated with reliability data that exceed a certain threshold. In response, the controller replaces these WLs with dummy WLs and programs data into the block using the dummy WLs instead.

Career Highlights

Attila A Herrera is currently employed at Micron Technology Incorporated, a leading company in the semiconductor industry. His work has been instrumental in enhancing the performance and reliability of memory systems.

Collaborations

Attila has collaborated with talented coworkers such as Tarun Singh Yadav and Scott Anthony Stoller, contributing to advancements in their field.

Conclusion

Attila A Herrera's innovative work in memory systems exemplifies the impact of adaptive technology on enhancing data reliability. His contributions continue to shape the future of memory component design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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