Kanagawa, Japan

Atsushi Kota

This inventor holds 3 USPTO granted patents. Top assignees: Nlt Technologies, Ltd., Samsung Led Co., Ltd.. Active years: 2004-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Atsushi Kota. Retrieved from https://idiyas.com/inventor/atsushi-kota-1cxhw67c

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Location History:

  • Kanagawa, JP (2004 - 2012)
  • Kawasaki, JP (2014)

Company Filing History:


Years Active: 2004-2014

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3 patents (USPTO):Explore Patents

Title: Innovations of Atsushi Kota in Image Display Technology

Introduction

Atsushi Kota is a notable inventor based in Kanagawa, Japan. He has made significant contributions to the field of image display technology, holding a total of 3 patents. His work focuses on enhancing the functionality and efficiency of timing controllers and image display devices.

Latest Patents

Atsushi Kota's latest patents include a timing controller, an image display device, and a timing signal generating method. The timing controller he developed is capable of achieving normal image display during reverse scanning in both upward and downward directions, as well as right and left directions. In his image display device, which incorporates multiple scanning line driving integrated circuits (ICs), a valid line counting section counts the number of valid driving lines based on the Data Enable (DE) signal and Dot Clock (DCK) signal. Additionally, a cascade signal counting section tracks the total count of outputs from the Vertical Clock (VCK) signals, including the Vertical Start Pulse (VSP) output signal, up to the VSP cascade outputting signal. The calculating section then determines any excessive output from the scanning line driving IC by comparing the count of valid driving lines with the total count of outputs. Finally, the VSP generating section produces a VSP signal that is time-shifted from the reference VSP generating time, allowing for effective reverse scanning.

Another patent focuses on a timing controller that ensures proper image display regardless of the scanning direction, even when using signal-line driving ICs with residual output terminals that are not connected to the signal lines. This timing controller features a reset signal storage section that holds various reset signals, including a normal reset signal and a specific reset signal. It also includes a reset signal setting section that selects one of the stored reset signals for each port based on external signals, and a reset signal synthesizing section that combines the selected reset signals with video data for simultaneous output to multiple ports.

Career Highlights

Atsushi Kota has worked with several prominent companies, including NLT Technologies and Samsung LED Co., Ltd. His experience in these organizations has contributed to his expertise in developing innovative technologies in the field of image display.

Collaborations

Atsushi has collaborated with notable colleagues such as Ju-won Lee and Cheol-sig Son. Their combined efforts have further advanced the research and development of image display technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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