Timing controller, image display device, timing signal generating method, and image display control method

Abstract

A timing controller is provided which is capable of achieving normal image display at a time of reverse scanning in upward and downward directions and right and left directions. In an image display device having a plurality of scanning line driving ICs (Integrated Circuits), a valid line counting section counts a count of valid driving lines based on a DE (Data Enable) signal and DCK (Dot Clock) signal. A cascade signal counting section counts up a total count of outputs from a count of VCK (Vertical Clock) signals including a VSP (Vertical Start Pulse)output signal up to a VSPcascade outputting signal VSP. A calculating section calculates an excessive output of a scanning line driving IC from a difference between the count of valid driving lines and the total count of outputs. A VSP generating section generates and outputs a VSPsignal at a time shifted from a reference VSP generating time by time being equivalent to the excessive output calculated by the calculating section thus enabling reverse scanning.