Chandler, AZ, United States of America

Arthur T Lowe

This inventor holds 1 USPTO granted patent. Top assignee: Motorola Corporation. Active years: 1986.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arthur T Lowe. Retrieved from https://idiyas.com/inventor/arthur-t-lowe-h0hd755u

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 15(Granted Patents)


Company Filing History:


Years Active: 1986

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1 patent (USPTO):Explore Patents

Title: Arthur T Lowe: Innovator in Semiconductor Technology

Introduction

Arthur T Lowe is a notable inventor based in Chandler, AZ (US). He has made significant contributions to the field of semiconductor technology, particularly in reducing gate leakage in devices. His innovative approach has implications for the efficiency and performance of electronic components.

Latest Patents

Arthur T Lowe holds a patent for "Fabricating a semiconductor device with reduced gate leakage." This invention addresses the issue of gate current leakage in submicron FET devices. By depositing an oxide layer over the gate prior to rapid heating, he prevents the dopant implanted into the gate from collecting on the sidewalls. This method effectively reduces the risk of current leakage from the gate to the source or drain, enhancing device reliability.

Career Highlights

Lowe is associated with Motorola Corporation, where he has applied his expertise in semiconductor fabrication. His work has contributed to advancements in the performance of electronic devices, making them more efficient and reliable.

Collaborations

Throughout his career, Arthur T Lowe has collaborated with notable colleagues, including Syd R Wilson and Schyi-Yi Wu. These partnerships have fostered innovation and have been instrumental in the development of new technologies in the semiconductor industry.

Conclusion

Arthur T Lowe's contributions to semiconductor technology exemplify the impact of innovative thinking in engineering. His patent for reducing gate leakage is a testament to his expertise and dedication to advancing electronic device performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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