Anil Nagori

Title: Anil Nagori: Innovator in Circuit Design Simulation

Introduction

Anil Nagori is a prominent inventor based in Santa Clara, CA, known for his contributions to the field of circuit design simulation. With a focus on enhancing the efficiency of parallel simulations, Nagori has made significant strides in optimizing circuit designs.

Latest Patents

Nagori holds a patent titled "Retiming a design for efficient parallel simulation." This innovative approach partitions circuit designs into pipeline regions, which include one or more pipeline levels. The method involves computing a path length for each combinational region within a pipeline region to establish achievable timing goals. A target retiming goal is then determined based on these computed goals. The process identifies pipeline regions that do not meet the target timing goal and computes a measure of slack for each pipeline level. Using this slack, the path lengths of combinational regions are iteratively retimed, resulting in a circuit design that can be simulated effectively if the retimed critical path meets the target timing goal.

Career Highlights

Anil Nagori is currently employed at Synopsys, Inc., where he continues to develop innovative solutions in circuit design. His work has been instrumental in advancing the capabilities of simulation technologies, making significant impacts in the industry.

Collaborations

Nagori collaborates with Ramesh Narayanaswamy, leveraging their combined expertise to push the boundaries of circuit design and simulation.

Conclusion

Anil Nagori's contributions to circuit design simulation exemplify the innovative spirit of modern engineering. His patent on retiming designs for efficient parallel simulation showcases his commitment to enhancing technology in this field.