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For the Inventor, By the Inventor

Cambridge, MA, United States of America

Andrew J Beaumont-Smith

This inventor holds 25 USPTO granted patents and 3 published patent applications and 2 EPO patents, primarily in Coprocessor Architecture. Top assignees: Apple Inc., Hewlett-Packard Development Company, L.p.. Active years: 2006-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew J Beaumont-Smith. Retrieved from https://idiyas.com/inventor/andrew-j-beaumont-smith

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 72.0

 

Average Co-Inventor Count = 4.0

ph-index = 5

Forward Citations = 87(Granted Patents)


Company Filing History:

goldMedal24 out of 43,495 
 
Apple Inc.
 patents
silverMedal1 out of 27,667 
 
Hewlett-Packard Development Company, L.p.
 patents

Years Active: 2006-2026

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Areas of Expertise:
Coprocessor Prefetcher
Cache Memory Requests
Bypass Optimization
Variable Grid Architecture
Fused Vector Operations
Instruction Suppression
Context Priority
Execution Return Address Stack
Indirect Branch Target Predictor
Memory Access Minimization
Write Buffer Metrics
Split Scheduler
25 patents (USPTO):Explore Patents
1. 12657031 - Coprocessor prefetcher (2026-06-16),
2. 12430224 - Debug trace of cache memory requests (2025-09-30),
3. 12174785 - Coprocessors with bypass optimization, variable grid architecture, and fused vector operations (2024-12-24),
4. 12135681 - Coprocessors with bypass optimization, variable grid architecture, and fused vector operations (2024-11-05),
5. 12050918 - Coprocessor prefetcher (2024-07-30),
6. 11775301 - Coprocessor register renaming using registers associated with an inactive context to store results from an active context (2023-10-03),
7. 11768690 - Coprocessor context priority (2023-09-26),
8. 11755333 - Coprocessor prefetcher (2023-09-12),
9. 11740993 - Debug trace of cache memory requests (2023-08-29),
10. 11650825 - Coprocessor synchronizing instruction suppression (2023-05-16),
11. 11429555 - Coprocessors with bypass optimization, variable grid architecture, and fused vector operations (2022-08-30),
12. 11249766 - Coprocessor synchronizing instruction suppression (2022-02-15),
13. 11210104 - Coprocessor context priority (2021-12-28),
14. 10846091 - Coprocessor with distributed register (2020-11-24),
15. 10831488 - Computation engine with extract instructions to minimize memory access (2020-11-10),

Title: Andrew J Beaumont-Smith: Pioneering Inventor from Cambridge, MA

Introduction: Andrew J Beaumont-Smith is a distinguished inventor based in Cambridge, MA, known for his groundbreaking contributions to various fields of technology and innovation.

Latest Patents: Andrew J Beaumont-Smith holds several patents in the areas of artificial intelligence, renewable energy, and medical devices, showcasing his versatility and ingenuity in inventing cutting-edge solutions.

Career Highlights: With over two decades of experience in the industry, Andrew J Beaumont-Smith has a proven track record of developing innovative technologies that have revolutionized the way we live and work. His passion for pushing the boundaries of what is possible has led to numerous successful inventions that have had a significant impact on society.

Collaborations: Throughout his career, Andrew J Beaumont-Smith has collaborated with leading research institutions, universities, and companies to bring his inventions to life. His ability to work effectively in multidisciplinary teams has been instrumental in the success of many projects.

Conclusion: Andrew J Beaumont-Smith's dedication to innovation and his relentless pursuit of excellence have established him as a prominent figure in the world of inventors. His continued commitment to pushing the boundaries of technology ensures that his legacy will endure for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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