Kyle, TX, United States of America

Andrew D Bettilyon

This inventor holds 1 USPTO granted patent. Top assignee: Cirrus Logic Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Andrew D Bettilyon. Retrieved from https://idiyas.com/inventor/andrew-d-bettilyon

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Andrew D. Bettilyon and Clock Integrity in Integrated Circuits.

Introduction

Andrew D. Bettilyon is an inventor associated with Kyle, Texas, and Cirrus Logic, Inc. His patent work addresses the integrity and protection of clock configurations in integrated circuits, particularly during security operations.

Latest Patents

The provided information lists one patent for Bettilyon: “Clock Integrity Verification and Protection in an Integrated Circuit (IC).” The invention describes an integrated circuit with multiple functional units and a reconfigurable clock management subsystem that supplies clock signals. A security subsystem prevents changes to the clock configuration while security operations are underway. Before those operations begin, the clock management subsystem checks clock integrity; if the check fails, the security operations do not proceed. Bettilyon is credited with 1 patent in the information provided.

Career Highlights

Bettilyon’s listed patent reflects work at the intersection of integrated-circuit design and hardware security. Its approach is designed to help ensure that security operations run only when the clock configuration passes an integrity check.

Collaborations

The provided information names Amar Vellanki and Brent W. Wilson as Bettilyon’s coworkers. It does not specify their roles in the patent or describe particular collaborations.

Conclusion

Andrew D. Bettilyon’s listed invention focuses on protecting clock integrity in integrated circuits, helping safeguard security operations against changes to clock configurations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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