The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Sep. 01, 2023
Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;
Amar Vellanki, Cedar Park, TX (US);
Brent W. Wilson, Austin, TX (US);
Andrew D. Bettilyon, Kyle, TX (US);
Wai-Shun Shum, Austin, TX (US);
Arun R. Ramani, Austin, TX (US);
Nathan D. P. Buchanan, Austin, TX (US);
CIRRUS LOGIC, INC., Austin, TX (US);
Abstract
An integrated circuit (IC), including multiple functional units for performing operations of the integrated circuit, provides security of a clock configuration at least during security operations. The IC includes a clock management subsystem for providing one or more clock signals to the functional units. The clock management subsystem is reconfigurable to adjust characteristics of the clock signal(s) or to select from among multiple clock sources from which the clock management subsystem generates the clock signal(s). The IC also includes a security subsystem for performing security operations within the IC and coupled to the clock management system to prevent alteration of a configuration of the clock management subsystem while the security operations are performed. The clock management subsystem performs a clock integrity check in response to the security operations before the security operations are performed. The security operations are not performed if the clock integrity check fails.