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Alexander D Peleg

This inventor holds 88 USPTO granted patents and 3 published patent applications and 1 EPO patent, primarily in Packed Data Processing (CPC class 395562). Top assignees: Intel Corporation, Other. Active years: 1979-2016.

USPTO Granted Patents = 88 (Patent Applications = 3)

% Patents Active = 62.5

EPO Patents = 1 (Patent Applications = 1)

Average Co-Inventor Count = 4.6

ph-index = 32

Forward Citations = 2,426(Granted Patents)

Forward Citations (Not Self Cited) = 1,976(Dec 10, 2025)

Inventors with similar research interests:

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Location History:

Moshav Bitzaron, by Gdera, IL (1979)
Near Gadera, IL (1989)
near Gedera, IL (1993)
Camelia, IL (2002)
Carmelia, IL (1997 - 2003)
Haifa, IL (1995 - 2016)

Company Filing History:

85 out of 56,240

Intel Corporation

patents

3 out of 834,411

Other

patents

Years Active: 1979-2016

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Areas of Expertise:

Packed Data

Saturation Packing

Multiply-Add Operations

Interleaving Techniques

Byte Elements

Data Registers

Sign Extension

Processor Architecture

Data Elements

Instruction Execution

Complex Numbers

88 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9389858 - Orderly storing of corresponding packed bytes from first and second source registers in result register (2016-07-12),

2. 9361100 - Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements (2016-06-07),

3. 9223572 - Interleaving half of packed data elements of size specified in instruction and stored in two source registers (2015-12-29),

4. 9182983 - Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers (2015-11-10),

5. 9141387 - Processor executing unpack and pack instructions specifying two source packed data operands and saturation (2015-09-22),

6. 9116687 - Packing in destination register half of each element with saturation from two source packed data registers (2015-08-25),

7. 9015453 - Packing odd bytes from two source registers of packed data (2015-04-21),

8. 8874882 - Compiler-directed sign/zero extension of a first bit size result to overwrite incorrect data before subsequent processing involving the result within an architecture supporting larger second bit size values (2014-10-28),

9. 8838946 - Packing lower half bits of signed data elements in two source registers in a destination register with saturation (2014-09-16),

10. 8793475 - Method and apparatus for unpacking and moving packed data (2014-07-29),

11. 8793299 - Processor for performing multiply-add operations on packed data (2014-07-29),

12. 8745119 - Processor for performing multiply-add operations on packed data (2014-06-03),

13. 8725787 - Processor for performing multiply-add operations on packed data (2014-05-13),

14. 8639914 - Packing signed word elements from two source registers to saturated signed byte elements in destination register (2014-01-28),

15. 8626814 - Method and apparatus for performing multiply-add operations on packed data (2014-01-07),

Title: Innovations and Contributions of Alexander D Peleg

Introduction

Alexander D Peleg, based in Haifa, Israel, is a prominent inventor with an impressive portfolio of 88 patents. His work primarily focuses on advancements in processor architecture and data handling techniques. His innovative solutions have significantly influenced the technology landscape.

Latest Patents

Among the latest patents attributed to Peleg are groundbreaking inventions that streamline data processing. One notable patent describes an apparatus for orderly storing corresponding packed bytes from first and second source registers into a result register. This invention features an instruction decoder that unpacks packed data upon receiving an unpack instruction. It meticulously arranges packed data elements to ensure efficient data handling.

Another significant patent from Peleg outlines a method for packing saturated lower 8-bit elements from two source registers of packed 16-bit elements. This design incorporates a processor with several registers that work collaboratively to decode packed instructions, optimizing how data elements are stored and processed, contributing to enhanced computational efficiency.

Career Highlights

Peleg's career includes pivotal roles at renowned companies, such as Intel Corporation, where he applied his expertise to develop advanced computing technologies. His innovations have made considerable impacts in the field of computer architecture and data processing methodologies.

Collaborations

Throughout his career, Alexander D Peleg has collaborated with esteemed colleagues, including Larry M Mennemeier and Benny Eitan. Their combined efforts have driven many of the innovative solutions and patents attributed to Peleg, showcasing the power of teamwork in technological advancements.

Conclusion

Alexander D Peleg's contributions to the field of technology through his numerous patents demonstrate his dedication to innovation. His work continues to inspire future advancements in data processing and processor architecture, reflecting his status as a leading inventor in the industry.

Profile summary based on public USPTO records.

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