Mountain View, CA, United States of America

Adam Wele

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Adam Wele. Retrieved from https://idiyas.com/inventor/adam-wele

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 9.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Adam Wele and His Patent in Software Transactional Memory

Introduction

Adam Wele is an inventor associated with Mountain View, California, and Intel Corporation. His patent work addresses concurrency control in software transactional memory systems.

Latest Patents

One patent attributed to Wele is “Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System.” It describes a method and apparatus that combines optimistic and pessimistic concurrency control in an STM system. A transaction record associated with a referenced memory address contains fields for both control approaches. Access barriers and other transactional operations maintain those fields, enabling optimistic and pessimistic transactions to execute concurrently. The supplied information lists 1 patent for Wele.

Career Highlights

Wele’s listed patent reflects work on coordinating concurrent transactions in software systems. The invention’s unified approach is designed to support both optimistic and pessimistic transaction handling within the same STM framework. He is associated with Intel Corporation.

Collaborations

The supplied information identifies Ali-Reza Adl-Tabatabai and James Henry Cownie as Wele’s coworkers. Their names are associated with his professional context, though specific roles in the patent are not provided.

Conclusion

Adam Wele’s patent focuses on enabling optimistic and pessimistic transactions to operate concurrently through unified control mechanisms in software transactional memory.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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