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For the Inventor, By the Inventor

Plano, TX, United States of America

Abhijeet Ashok Chachad

This inventor holds 122 USPTO granted patents and 29 published patent applications and 2 EPO patents, primarily in Cache Management (CPC class G06F12-0811). Top assignee: Texas Instruments Corporation. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Abhijeet Ashok Chachad. Retrieved from https://idiyas.com/inventor/abhijeet-ashok-chachad

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 122 

% Patents Active = 94.3

 

Average Co-Inventor Count = 3.5

ph-index = 7

Forward Citations = 297(Granted Patents)

Forward Citations (Not Self Cited) = 223(Dec 10, 2025)


Inventors with similar research interests:

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Company Filing History:

goldMedal122 out of 29,888 
 
Texas Instruments Corporation
 patents

Years Active: 2007-2026

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Areas of Expertise:
Cache Management
Pipeline Arbitration
Multi-Master Memory
Error Correcting Codes
Prefetch Management
Hardware Coherence
Memory Controller
Hierarchical Cache
Multicore Architecture
Streaming Engine
Non-Correctable Errors
Cache Security
122 patents (USPTO):Explore Patents
1. 12762058 - Aliased mode for cache controller (2026-10-13),
2. 12699589 - Global coherence operations (2026-08-04),
3. 12675312 - Pseudo-random way selection (2026-07-07),
4. 12625815 - Memory pipeline control in a hierarchical memory system (2026-05-12),
5. 12625809 - Cache coherence shared state suppression (2026-05-12),
6. 12619457 - Merging data for write allocate (2026-05-05),
7. 12613731 - Pipeline arbitration (2026-04-28),
8. 12578963 - Implied fence on stream open (2026-03-17),
9. 12572416 - Error correcting codes for multi-master memory controller (2026-03-10),
10. 12572360 - Cache preload operations using streaming engine (2026-03-10),
11. 12561255 - Prefetch kill and revival in an instruction cache (2026-02-24),
12. 12524351 - Lookahead priority collection to support priority elevation (2026-01-13),
13. 12517830 - Write streaming with cache write acknowledgment in a processor (2026-01-06),
14. 12505015 - Pipelined read-modify-write operations in cache memory (2025-12-23),
15. 12493522 - Write control for read-modify-write operations in cache memory (2025-12-09),

Title: Abhijeet Ashok Chachad: Revolutionizing Industries with Innovative Solutions

Introduction:

Throughout his illustrious career, Abhijeet Ashok Chachad has established himself as an expert in developing groundbreaking solutions across various industries. With an impressive number of patents under his belt, Chachad has made significant contributions to technology, healthcare, and consumer electronics. This article delves into the latest patents by Chachad, highlights his career achievements, and explores his collaborations with notable individuals.

Latest Patents:

Abhijeet Ashok Chachad's recent patents showcase his forward-thinking approach and technological prowess. One notable invention is the "Cache Size Change" method. This innovation involves dynamically adjusting the size of a level one (L1) main cache, optimizing efficiency and performance. Additionally, Chachad's "Multicore Bus Architecture with Wire Reduction and Physical Congestion Minimization via Shared Transaction Channels" patent introduces a novel technique for utilizing shared channels, resulting in improved data transmission and minimized physical congestion.

Career Highlights:

With an impressive track record, Chachad has been associated with esteemed companies such as Texas Instruments Corporation and Texas Instruments Incorporated, where he has honed his expertise in developing cutting-edge solutions. His career highlights include spearheading projects in technology, healthcare, and consumer electronics, showcasing his versatility and adaptability to different industries.

Collaborations:

Chachad's commitment to innovation extends beyond solo endeavors, as evidenced by his collaborations with industry experts. Notably, he has collaborated with David Matthew Thompson and Timothy David Anderson, aligning their collective expertise to drive transformative solutions. These collaborations highlight Chachad's proficiency in working as part of a team while leveraging diverse skill sets to achieve remarkable results.

Conclusion:

Abhijeet Ashok Chachad's exceptional expertise and innovative mindset have made significant contributions to multiple industries. His latest patents, including the cache size change method and the multicore bus architecture, are testament to his invaluable contributions in enhancing efficiency and performance. With a successful career marked by notable collaborations, Chachad continues to shape the future of technology, healthcare, and consumer electronics with his groundbreaking solutions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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