The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Jan. 29, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Timothy David Anderson, University Park, TX (US);

David Matthew Thompson, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 1/14 (2006.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 12/0811 (2016.01); G06F 12/0842 (2016.01); G06F 12/0888 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0842 (2013.01); G06F 1/14 (2013.01); G06F 9/38 (2013.01); G06F 9/544 (2013.01); G06F 12/0811 (2013.01); G06F 12/0888 (2013.01); G06F 2212/1016 (2013.01);
Abstract

In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.


Find Patent Forward Citations

Loading…