Abdalla Aly Naem

This inventor holds 29 USPTO granted patents, primarily in Semiconductor Devices. Top assignee: National Semiconductor Corporation. Active years: 2000-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Abdalla Aly Naem. Retrieved from https://idiyas.com/inventor/abdalla-aly-naem

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29

% Patents Active = 100.0

Average Co-Inventor Count = 1.1

ph-index = 6

Forward Citations = 145(Granted Patents)

Location History:

Overisje, BE (2000)
Brussels, BE (2002)
Overiise, BE (2003 - 2004)
Overijse, BE (2002 - 2006)
San Jose, CA (US) (2010 - 2012)

Company Filing History:

29 out of 4,791

National Semiconductor Corporation

patents

Years Active: 2000-2012

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Areas of Expertise:

Bipolar Transistor

MOSFET Design

Copper Interconnects

Silicon Germanium

Laser Annealing

Doped Silicon-Germanium

Dual-Sided Device

Transistor Architecture

Thin Copper Traces

Stacked Die Structure

Conductive Path

29 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8324097 - Method of forming a copper topped interconnect structure that has thin and thick copper traces (2012-12-04),

2. 8318563 - Growth of group III nitride-based structures and integration with conventional CMOS processing tools (2012-11-27),

3. 8273608 - Method of forming a copper-compatible fuse target (2012-09-25),

4. 8030733 - Copper-compatible fuse target (2011-10-04),

5. 7964934 - Fuse target and method of forming the fuse target in a copper process flow (2011-06-21),

6. 7847385 - Stacked die structure with an underlying copper-topped die (2010-12-07),

7. 7709956 - Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure (2010-05-04),

8. 7118973 - Method of forming a transistor with a channel region in a layer of composite material (2006-10-10),

9. 7115973 - Dual-sided semiconductor device with a resistive element that requires little silicon surface area (2006-10-03),

10. 7098095 - Method of forming a MOS transistor with a layer of silicon germanium carbon (2006-08-29),

11. 7087979 - Bipolar transistor with an ultra small self-aligned polysilicon emitter (2006-08-08),

12. 6853017 - Bipolar transistor structure with ultra small polysilicon emitter (2005-02-08),

13. 6818938 - MOS transistor and method of forming the transistor with a channel region in a layer of composite material (2004-11-16),

14. 6784099 - Dual-sided semiconductor device and method of forming the device with a resistive element that requires little silicon surface area (2004-08-31),

15. 6784065 - Bipolar transistor with ultra small self-aligned polysilicon emitter and method of forming the transistor (2004-08-31),

Title: Innovations by Abdalla Aly Naem: Pioneering Contributions to Semiconductor Technology

Introduction

Abdalla Aly Naem is an accomplished inventor based in Overijse, Belgium, with an impressive portfolio of 29 patents. His innovative work primarily focuses on semiconductor technologies, where he has contributed significantly to the development of methods that enhance device performance and integration.

Latest Patents

Among his latest patents is a groundbreaking method for forming a copper-topped interconnect structure that features both thin and thick copper traces. This innovation allows for high-density design areas with low current requirements, utilizing tightly packed thin traces, alongside low-density areas that cater to high current demands with thicker, wider traces. This dual-approach enhances the flexibility and efficiency of chip design.

Another noteworthy patent emphasizes the growth of group III nitride-based structures, which integrate seamlessly with conventional CMOS processing tools. This method revolves around forming a non-continuous epitaxial layer over a semiconductor substrate with multiple mesas separated by trenches. It includes depositing dielectric material in the trenches and involves advanced fabrication techniques that can leverage standard silicon processing tools.

Career Highlights

Abdalla Aly Naem is currently associated with National Semiconductor Corporation, where he has collaborated with a team of skilled professionals to push the boundaries of semiconductor technology. His career is marked by a strong emphasis on innovation and practical applications of complex engineering principles.

Collaborations

Throughout his career, Abdalla has worked closely with notable colleagues such as Stepan Essaian and Reda R Razouk. Their collaborative efforts have led to significant advancements in the semiconductor field, particularly in the realm of chip design and fabrication methodologies.

Conclusion

Abdalla Aly Naem’s contributions to semiconductor technology through his numerous patents highlight his role as a leading innovator in the industry. His work not only enhances the performance of current devices but also sets the groundwork for future advancements in technology. With a robust career and continued collaborations, Abdalla remains a vital figure in the realm of innovative inventions.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]