For the Inventor, By the Inventor

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Tarrytown, NY, United States of America

Optimum Semiconductor Technologies Inc.

USPTO Granted Patents = 25

% Expired Patents = 8.0

EPO Patents = 9

Forward Citations = 125

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20 inventors (with patents filed for the assignee):

Mayan Moudgill (20 out of 61 patents)

Gary J Nacer (16 out of 18 patents)

C John Glossner (16 out of 33 patents)

4. Murugappan Senthilvelan (13 out of 14 patents)

5. Arthur Joseph Hoane (12 out of 15 patents)

6. Paul Hurtley (12 out of 12 patents)

7. Pablo Balzola (9 out of 14 patents)

8. Vitaly Kalashnikov (7 out of 8 patents)

9. A Joseph Hoane (6 out of 6 patents)

10. Sitij Agrawal (5 out of 8 patents)

11. Sabin Daniel Iancu (3 out of 3 patents)

12. Shenghong Wang (3 out of 16 patents)

13. John Glossner (3 out of 13 patents)

14. Paul Gerard D'Arcy (2 out of 18 patents)

15. Lei Wang (1 out of 580 patents)

Core Competencies:

Neural Network

Accelerator

Vector Processor

Multithreading

Graphics Processing

Variable Length Vectors

Pipeline Control

Digital Signal Processing

Atomic Primitives

Video Stabilization

Cache Line Locking

Translation-Lookaside Buffer

25 patents: Sort by Forward Citations

1. 12632257 - System and architecture neural network accelerator including filter circuit (2026-05-19),

2. 12602229 - Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage (2026-04-14),

3. 11650817 - System and method to implement masked vector instructions (2023-05-16),

4. 11544214 - Monolithic vector processor configured to operate on variable length vectors using a vector length register (2023-01-03),

5. 11157407 - Implementing atomic primitives using cache line locking (2021-10-26),

6. 11144815 - System and architecture of neural network accelerator (2021-10-12),

7. 10922267 - Vector processor to operate on variable length vectors using graphics processing instructions (2021-02-16),

8. 10908909 - Processor with mode support (2021-02-02),

9. 10846259 - Vector processor to operate on variable length vectors with out-of-order execution (2020-11-24),

10. 10824586 - Vector processor configured to operate on variable length vectors using one or more complex arithmetic instructions (2020-11-03),

11. 10733140 - Vector processor configured to operate on variable length vectors using instructions that change element widths (2020-08-04),

12. 10719451 - Variable translation-lookaside buffer (TLB) indexing (2020-07-21),

13. 10514915 - Computer processor with address register file (2019-12-24),

14. 10381725 - Monolithic dual band antenna (2019-08-13),

15. 10339095 - Vector processor configured to operate on variable length vectors using digital signal processing instructions (2019-07-02),

Company Overview

Optimum Semiconductor Technologies Inc. is a technology company based in Tarrytown, NY, specializing in advanced semiconductor solutions. The organization focuses on the development and manufacturing of high-performance semiconductor devices that cater to various applications, including consumer electronics, telecommunications, and automotive sectors. With a commitment to innovation, Optimum Semiconductor leverages cutting-edge research in materials science and electronic engineering to enhance the efficiency and functionality of its products.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

25 Patents

#13 in Tarrytown, NY

#788 in New York

#13,364 in US

#25,710 in the World

Tarrytown, NY, United States of America

Optimum Semiconductor Technologies Inc.

Forward Citations = 125

20 inventors:

Mayan Moudgill (20 out of 61 patents)

Gary J Nacer (16 out of 18 patents)

C John Glossner (16 out of 33 patents)

4. Murugappan Senthilvelan (13 out of 14 patents)

5. Arthur Joseph Hoane (12 out of 15 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Optimum Semiconductor Technologies Inc.. Retrieved from https://idiyas.com/company/optimum-semiconductor-technologies

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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