For the Inventor, By the Inventor

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Chongqing, China

No. 24 Research Institute of China Electronic Technology Corporation

USPTO Granted Patents = 3

Forward Citations = 0

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22 inventors (with patents filed for the assignee):

Dongbing Fu (3 out of 37 patents)

Guangbing Chen (3 out of 35 patents)

Yuxin Wang (3 out of 20 patents)

4. Gangyi Hu (2 out of 19 patents)

5. Ruzhang Li (2 out of 22 patents)

6. Xiaofeng Shen (1 out of 9 patents)

7. Ting Li (1 out of 23 patents)

8. Yong Zhang (1 out of 21 patents)

9. Zhengping Zhang (1 out of 9 patents)

10. Yan Wang (1 out of 13 patents)

11. Jie Pu (1 out of 5 patents)

12. Youhua Wang (1 out of 4 patents)

13. Lu Liu (1 out of 7 patents)

14. Xu Wang (1 out of 6 patents)

15. Rongbin Hu (1 out of 6 patents)

3 patents: Sort by Forward Citations

1. 10404243 - Clock delay adjusting circuit based on edge addition and integrated chip thereof (2019-09-03),

2. 10291245 - Device and method for correcting error estimation of analog-to-digital converter (2019-05-14),

3. 9455735 - High speed sampling front-end circuit (2016-09-27),

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USPTO Data Jan 1 1976 - Dec 16 2025

3 Patents

#71 in Chongqing

#7,218 in China

Chongqing, China

No. 24 Research Institute of China Electronic Technology Corporation

Forward Citations = 0

22 inventors:

Dongbing Fu (3 out of 37 patents)

Guangbing Chen (3 out of 35 patents)

Yuxin Wang (3 out of 20 patents)

4. Gangyi Hu (2 out of 19 patents)

5. Ruzhang Li (2 out of 22 patents)

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