The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Aug. 20, 2015
Applicant:

No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing, CN;

Inventors:

Jie Pu, Chongqing, CN;

Gangyi Hu, Chongqing, CN;

Xiaofeng Shen, Chongqing, CN;

Xueliang Xu, Chongqing, CN;

Dongbing Fu, Chongqing, CN;

Ruitao Zhang, Chongqing, CN;

Youhua Wang, Chongqing, CN;

Yuxin Wang, Chongqing, CN;

Guangbing Chen, Chongqing, CN;

Ruzhang Li, Chongqing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0609 (2013.01); H03M 1/10 (2013.01);
Abstract

The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.


Find Patent Forward Citations

Pu, Jie. (2019). Device and method for correcting error estimation of analog-to-digital converter (U.S. Patent No. 10291245). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10291245

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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