For the Inventor, By the Inventor

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Irvine, CA, United States of America

Netlogic Microsystems, Inc

USPTO Granted Patents = 456

% Expired Patents = 61.2

EPO Patents = 2

Trademarks = 3

Forward Citations = 8,794

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190 inventors (with patents filed for the assignee):

Varadarajan Srinivasan (109 out of 126 patents)

Sandeep Khanna (104 out of 127 patents)

Bindiganavale S Nataraj (70 out of 75 patents)

4. Jose Pio Pereira (43 out of 116 patents)

5. David T Hass (25 out of 56 patents)

6. Srinivasan Venkatachary (24 out of 47 patents)

7. Pankaj Gupta (20 out of 35 patents)

8. Dinesh Maheshwari (17 out of 73 patents)

9. Chetan Deshpande (16 out of 28 patents)

10. Stefanos Sidiropoulos (16 out of 98 patents)

11. Maheshwaran Srinivasan (16 out of 16 patents)

12. Dimitri Argyres (15 out of 17 patents)

13. Michael E Ichiriu (14 out of 15 patents)

14. Mark Birman (13 out of 17 patents)

15. Marc Loinaz (13 out of 24 patents)

Core Competencies:

Content Addressable Memory

Network Processing

Power Management

Packet Scheduling

Error Reporting

Signal Filtering

Data Flow Management

Echo Cancellation

Memory Management

Processor Architecture

Traffic Shaping

Multi-Core Processing

456 patents: Sort by Forward Citations

1. 9069564 - Weighted instruction count scheduling (2015-06-30),

2. 8990631 - Packet format for error reporting in a content addressable memory (2015-03-24),

3. 8990422 - TCP segmentation offload (TSO) using a hybrid approach of manipulating memory pointers and actual packet data (2015-03-24),

4. 8982596 - Content addressable memory having column segment redundancy (2015-03-17),

5. 8964905 - Low power serial link (2015-02-24),

6. 8953628 - Processor with packet ordering device (2015-02-10),

7. 8949522 - Performance of a stride-based prefetcher on an out-of-order processing unit (CPU) (2015-02-03),

8. 8948331 - Systems, circuits and methods for filtering signals to compensate for channel effects (2015-02-03),

9. 8943236 - Packet scheduling using a programmable weighted fair queuing scheduler that employs deficit round robin (2015-01-27),

10. 8935270 - Content search system including multiple deterministic finite automaton engines having shared memory resources (2015-01-13),

11. 8923384 - System, method and device for processing macroblock video data (2014-12-30),

12. 8917582 - Analog echo canceller with interpolating output (2014-12-23),

13. 8913412 - Incremental adaptive match line charging with calibration (2014-12-16),

14. 8901909 - Multi-phase power system with redundancy (2014-12-02),

15. 8886677 - Integrated search engine devices that support LPM search operations using span prefix masks that encode key prefix length (2014-11-11),

Company Overview

Netlogic Microsystems, Inc., based in Irvine, California, specializes in advanced content addressable memory technologies. The company focuses on developing solutions that enhance network processing capabilities, optimize power management, and improve data flow management. Their expertise extends to critical areas such as packet scheduling, error reporting, signal filtering, and echo cancellation, positioning them as a key player in the semiconductor industry. Netlogic's innovations aim to address the growing demands of high-performance computing and networking applications.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

456 Patents

#9 in Irvine, CA

#227 in California

#1,053 in US

#2,093 in the World

Irvine, CA, United States of America

Netlogic Microsystems, Inc

Forward Citations = 8,794

190 inventors:

Varadarajan Srinivasan (109 out of 126 patents)

Sandeep Khanna (104 out of 127 patents)

Bindiganavale S Nataraj (70 out of 75 patents)

4. Jose Pio Pereira (43 out of 116 patents)

5. David T Hass (25 out of 56 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Netlogic Microsystems, Inc. Retrieved from https://idiyas.com/company/netlogic-microsystems

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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