For the Inventor, By the Inventor

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Mountain View, CA, United States of America

Netlogic Microsystems, Inc

USPTO Granted Patents = 456

EPO Patents = 2

Trademarks = 3

Forward Citations = 8,710

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190 inventors (with patents filed for the assignee):

Varadarajan Srinivasan (109 out of 125 patents)

Sandeep Khanna (104 out of 126 patents)

Bindiganavale S Nataraj (70 out of 74 patents)

4. Jose Pio Pereira (43 out of 116 patents)

5. David T Hass (25 out of 56 patents)

6. Srinivasan Venkatachary (24 out of 47 patents)

7. Pankaj Gupta (20 out of 35 patents)

8. Dinesh Maheshwari (17 out of 71 patents)

9. Chetan Deshpande (16 out of 28 patents)

10. Stefanos Sidiropoulos (16 out of 97 patents)

11. Maheshwaran Srinivasan (16 out of 16 patents)

12. Dimitri Argyres (15 out of 17 patents)

13. Michael E Ichiriu (14 out of 15 patents)

14. Mark Birman (13 out of 17 patents)

15. Marc Loinaz (13 out of 24 patents)

Core Competencies:

Content Addressable Memory

Packet Scheduling

TCP Segmentation Offload

Power Control

Data Flow Management

Network Processor

Echo Cancellation

Video Data Processing

Memory Signaling

Multi-Chip Environment

Adaptive Linearization

Clock Synthesis

456 patents: Sort by Forward Citations

1. 9069564 - Weighted instruction count scheduling (2015-06-30),

2. 8990631 - Packet format for error reporting in a content addressable memory (2015-03-24),

3. 8990422 - TCP segmentation offload (TSO) using a hybrid approach of manipulating memory pointers and actual packet data (2015-03-24),

4. 8982596 - Content addressable memory having column segment redundancy (2015-03-17),

5. 8964905 - Low power serial link (2015-02-24),

6. 8953628 - Processor with packet ordering device (2015-02-10),

7. 8949522 - Performance of a stride-based prefetcher on an out-of-order processing unit (CPU) (2015-02-03),

8. 8948331 - Systems, circuits and methods for filtering signals to compensate for channel effects (2015-02-03),

9. 8943236 - Packet scheduling using a programmable weighted fair queuing scheduler that employs deficit round robin (2015-01-27),

10. 8935270 - Content search system including multiple deterministic finite automaton engines having shared memory resources (2015-01-13),

11. 8923384 - System, method and device for processing macroblock video data (2014-12-30),

12. 8917582 - Analog echo canceller with interpolating output (2014-12-23),

13. 8913412 - Incremental adaptive match line charging with calibration (2014-12-16),

14. 8901909 - Multi-phase power system with redundancy (2014-12-02),

15. 8886677 - Integrated search engine devices that support LPM search operations using span prefix masks that encode key prefix length (2014-11-11),

NetLogic Microsystems, Inc is a leading provider of intelligent semiconductor solutions that are powering next-generation Internet networks. The company's innovative products enable the design and development of advanced networking systems for data centers, enterprise networks, and wireless infrastructure. With a focus on high-performance deep packet processing, knowledge-based processing, and network search engines, NetLogic Microsystems delivers technology solutions that enhance network performance, security, and efficiency.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Dec 30 2025

456 Patents

#10 in Mountain View, CA

#232 in California

#1,008 in US

#2,021 in the World

Mountain View, CA, United States of America

Netlogic Microsystems, Inc

Forward Citations = 8,710

190 inventors:

Varadarajan Srinivasan (109 out of 125 patents)

Sandeep Khanna (104 out of 126 patents)

Bindiganavale S Nataraj (70 out of 74 patents)

4. Jose Pio Pereira (43 out of 116 patents)

5. David T Hass (25 out of 56 patents)

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