For the Inventor, By the Inventor

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San Jose, CA, United States of America

Exponential Technology, Inc.

Calculating rank

USPTO Granted Patents = 34

Forward Citations = 2,288

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14 inventors (with patents filed for the assignee):

James S Blomgren (24 out of 39 patents)

Earl T Cohen (15 out of 154 patents)

David E Richter (9 out of 14 patents)

4. Jay C Pattin (6 out of 6 patents)

5. Cheryl Senter Brashears (4 out of 4 patents)

6. Shalesh Thusoo (2 out of 20 patents)

7. Frederick Buckley, Iii (2 out of 3 patents)

8. Siegfried Wiedmann (2 out of 2 patents)

9. Russell W Tilleman (2 out of 2 patents)

10. Brian R Baird (1 out of 15 patents)

11. Scott H McMahon (1 out of 4 patents)

12. Gene Shen (1 out of 3 patents)

13. Louis S Lederer (1 out of 1 patent)

14. Peter J Vigil (1 out of 2 patents)

Core Competencies:

Processor Architecture

Dual-Instruction-Set

Cache Systems

Branch Prediction

Floating Point

Multi-Processor

ALU

Debug Breakpoints

RAM

Instruction Decoding

Pipelined Processor

34 patents: Sort by Forward Citations

1. 5884057 - Temporal re-alignment of a floating point pipeline to an integer (1999-03-16),

2. 5809272 - Early instruction-length pre-decode of variable-length instructions in a (1998-09-15),

3. 5784590 - Slave cache having sub-line valid bits updated by a master cache (1998-07-21),

4. 5781750 - Dual-instruction-set architecture CPU with hidden software emulation mode (1998-07-14),

5. 5781457 - Merge/mask, rotate/shift, and boolean operations from two instruction (1998-07-14),

6. 5757690 - Embedded ROM with RAM valid bits for fetching ROM-code updates from (1998-05-26),

7. 5751614 - Sign-extension merge/mask, rotate/shift, and boolean operations executed (1998-05-12),

8. 5745913 - Multi-processor DRAM controller that prioritizes row-miss requests to (1998-04-28),

9. 5732209 - Self-testing multi-processor die with internal compare points (1998-03-24),

10. 5692152 - Master-slave cache system with de-coupled data and tag pipelines and (1997-11-25),

11. 5687336 - Stack push/pop tracking and pairing in a pipelined processor (1997-11-11),

12. 5685009 - Shared floating-point registers and register port-pairing in a (1997-11-04),

13. 5664159 - Method for emulating multiple debug breakpoints by page partitioning (1997-09-02),

14. 5652872 - Translator having segment bounds encoding for storage in a TLB (1997-07-29),

15. 5644752 - Combined store queue for a master-slave cache system (1997-07-01),

Company Overview

Exponential Technology, Inc., based in San Jose, CA, specializes in advanced technology solutions that drive innovation across various sectors. The company focuses on developing cutting-edge software and hardware systems, with a strong emphasis on artificial intelligence, machine learning, and automation. By leveraging its expertise, Exponential Technology aims to enhance operational efficiencies and create transformative products that meet the evolving needs of industries worldwide.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

34 Patents

#243 in San Jose, CA

#2,381 in California

#10,028 in US

#19,664 in the World

San Jose, CA, United States of America

Exponential Technology, Inc.

Forward Citations = 2,288

14 inventors:

James S Blomgren (24 out of 39 patents)

Earl T Cohen (15 out of 154 patents)

David E Richter (9 out of 14 patents)

4. Jay C Pattin (6 out of 6 patents)

5. Cheryl Senter Brashears (4 out of 4 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Exponential Technology, Inc.. Retrieved from https://idiyas.com/company/exponential-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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