Slave cache having sub-line valid bits updated by a master cache

Abstract

A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slave caches, freeing the slaves of these bandwidth-robbing duties. Only the slave caches store sub-line valid bits with all cache lines; the master cache has only full cache lines valid. During a miss from a slave cache, the slave cache sends its sub-line valid bits to the master cache. The slave's sub-line valid bits are loaded into a request pipeline in the master cache. As requests are fulfilled and finish the pipeline, its address is compared to the addresses of all other pending requests in the master's pipeline. If another pending request matches the slave's index and tag, its sub-line valid bits are updated by setting the corresponding sub-line valid bit for the completing request's sub-line. If another pending request matches the slave's index but not the tag, all of the other request's sub-line valid bits are cleared. Thus subline valid bits of pending requests are updated as each request completes the master's pipeline and writes its sub-line to the slave cache.