The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Mar. 16, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Tatsufumi Hamada, Yokkaichi, JP;

Shinya Naito, Toyota, JP;

Hiroshi Kanno, Yokkaichi, JP;

Yoshiaki Fukuzumi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11582 (2013.01); H01L 29/1037 (2013.01); H01L 27/11519 (2013.01); H01L 27/11565 (2013.01); H01L 29/42368 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a base semiconductor layer, first and second conductive layers, a semiconductor body, a memory layer, first and second semiconductor regions, and an insulating portion. The first conductive layer is separated from the base semiconductor layer in a first direction. The second conductive layer is provided between the base semiconductor layer and the first conductive layer. The semiconductor body extends through the first conductive layer in the first direction. The memory layer is provided between the semiconductor body and the first conductive layer. The first semiconductor region is provided between the memory layer and the base semiconductor layer and between the semiconductor body and the base semiconductor layer, and is of a first conductivity type. The second semiconductor region is provided between the first semiconductor region and the memory layer, and is of a second conductivity type.


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