The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2018

Filed:

Mar. 30, 2015
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Namit K. Gupta, San Jose, CA (US);

Jean-Marc A. Forey, Grenoble, FR;

Mahantesh D. Narwade, Mountain View, CA (US);

Horia A. Toma, Sunnyvale, CA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G01R 31/317 (2013.01); G06F 17/5081 (2013.01); G06F 2217/14 (2013.01); G06F 2217/84 (2013.01);
Abstract

Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.


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