The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jan. 08, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Ling Lin, Kaohsiung, TW;

Chih-Sen Huang, Tainan, TW;

Ching-Wen Hung, Tainan, TW;

Jia-Rong Wu, Kaohsiung, TW;

Tsung-Hung Chang, Yunlin County, TW;

Yi-Hui Lee, Taipei, TW;

Yi-Wei Chen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01); H01L 21/823475 (2013.01); H01L 23/53261 (2013.01); H01L 23/53266 (2013.01); H01L 27/0629 (2013.01); H01L 21/76829 (2013.01);
Abstract

A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.


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