The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2018

Filed:

May. 03, 2017
Applicants:

Sanken Electric Co., Ltd, Niiza-shi, Saitama, JP;

Shin-etsu Handotai Co. Ltd., Tokyo, JP;

Inventors:

Hiroshi Shikauchi, Niiza, JP;

Ken Sato, Miyoshi-machi, JP;

Hirokazu Goto, Minato-ku, JP;

Masaru Shinomiya, Annaka, JP;

Keitaro Tsuchiya, Takasaki, JP;

Kazunori Hagimoto, Takasaki, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/36 (2006.01); H01L 21/225 (2006.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); C30B 29/40 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02658 (2013.01); C30B 25/186 (2013.01); C30B 29/06 (2013.01); C30B 29/403 (2013.01); H01L 21/0245 (2013.01); H01L 21/0254 (2013.01); H01L 21/0259 (2013.01); H01L 21/02381 (2013.01); H01L 21/2251 (2013.01); H01L 29/36 (2013.01); H01L 21/02595 (2013.01); H01L 21/02598 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01);
Abstract

A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×10atoms/cmor more and less than 1×10atoms/cm. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.


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