The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Nov. 19, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Jianbo Yang, Singapore, SG;

Ling Wu, Singapore, SG;

Sung Mun Jung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H01L 21/26513 (2013.01);
Abstract

Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.


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