The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2018

Filed:

Jul. 05, 2016
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Yung-Jen Chen, Kaohsiung, TW;

Yi-Chuan Ding, Kaohsiung, TW;

Min-Lung Huang, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/486 (2013.01); H01L 21/768 (2013.01); H01L 23/3157 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/06 (2013.01); H01L 24/19 (2013.01); H01L 24/29 (2013.01); H01L 24/96 (2013.01); H01L 21/56 (2013.01); H01L 21/76877 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01);
Abstract

In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.


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