The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Jul. 19, 2013
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Chih-Yu Hsu, Xinfeng Township, TW;
Yi-Tang Lin, Hsin-Chu, TW;
Clement Hsinjen Wann, Carmel, NY (US);
Chih-Sheng Chang, Hsin-Chu, TW;
Wei-Chun Tsai, Hsin-Chu, TW;
Jyh-Cherng Sheu, Hsin-Chu, TW;
Chi-Yuan Shih, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.