The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2018
Filed:
Feb. 04, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Yu-Lien Huang, Jhubei, TW;
Tung Ying Lee, Hsin-Chu, TW;
Pei-Yi Lin, Taichung, TW;
Chun-Hsiang Fan, Hsin-Chu, TW;
Sheng-Wen Yu, New Taipei, TW;
Neng-Kuo Chen, Hsin-Chu, TW;
Ming-Huan Tsai, Zhubei, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/8234 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/324 (2006.01); H01L 27/088 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/31055 (2013.01); H01L 21/324 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 27/088 (2013.01); H01L 29/401 (2013.01);
Abstract
A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.