The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Sep. 22, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Keith Alan Bowman, Morrisville, NC (US);

Francois Ibrahim Atallah, Raleigh, NC (US);

David Joseph Winston Hansquine, Raleigh, NC (US);

Jihoon Jeong, Cary, NC (US);

Hoan Huu Nguyen, Durham, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/04 (2006.01); G11C 11/40 (2006.01); H03K 19/003 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
G11C 15/04 (2013.01); G11C 11/40 (2013.01); H03K 19/00315 (2013.01); H03K 19/094 (2013.01);
Abstract

Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage/value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.


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