The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Dec. 17, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nachiket R. Raravikar, Gilbert, AZ (US);

James C. Matayabas, Jr., Gilbert, AZ (US);

Akshay Mathkar, Tempe, AZ (US);

Dingying Xu, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01R 43/20 (2006.01); G01R 1/073 (2006.01);
U.S. Cl.
CPC ...
H01R 43/20 (2013.01); G01R 1/07378 (2013.01);
Abstract

Space transformer including a substrate and a perforated plate disposed on the substrate. The substrate includes conductive traces and an array of conductive probe pins extend outwardly from anchor points on the substrate. The pins are electrically coupled to at least one of the conductive traces on the substrate as an interface between an E-testing apparatus and a DUT. The perforated plate may be affixed to a surface of the substrate and includes an array of perforations through which the conductive pins may pass. The perforated plate may provide one or more of lateral pin support and protection to the underlying substrate and/or traces. The perforated plate may include a metal sheet. A polymeric material may be disposed on at least a sidewall of the perforations to electrically isolate the metal sheet from the conductive probe pins.


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