The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Feb. 03, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yoshiaki Fukuzumi, Kanagawa-ken, JP;

Ryota Katsumata, Kanagawa-ken, JP;

Masaru Kito, Kanagawa-ken, JP;

Masaru Kidoh, Tokyo, JP;

Hiroyasu Tanaka, Tokyo, JP;

Yosuke Komori, Kanagawa-ken, JP;

Megumi Ishiduki, Kanagawa-ken, JP;

Junya Matsunami, Kanagawa-ken, JP;

Tomoko Fujiwara, Kanagawa-ken, JP;

Hideaki Aochi, Kanagawa-ken, JP;

Ryouhei Kirisawa, Kanagawa-ken, JP;

Yoshimasa Mikajiri, Kanagawa-ken, JP;

Shigeto Oota, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/265 (2006.01); H01L 21/223 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/223 (2013.01); H01L 21/265 (2013.01); H01L 29/1037 (2013.01); H01L 29/42344 (2013.01); H01L 29/4916 (2013.01);
Abstract

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.


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