The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

May. 08, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Haiting Wang, Clifton Park, NY (US);

Wei Zhao, Fort Lee, NJ (US);

Hong Yu, Rexford, NY (US);

Xusheng Wu, Ballston Lake, NY (US);

Hui Zang, Guilderland, NY (US);

Zhenyu Hu, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 29/06 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/02164 (2013.01); H01L 21/3086 (2013.01); H01L 21/31111 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01);
Abstract

Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.


Find Patent Forward Citations

Wang, Haiting. (2018). Fin-type field effect transistors with single-diffusion breaks and method (U.S. Patent No. 9935104). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9935104

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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