The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Feb. 23, 2016
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Grzegorz Mrugalski, Swarzedz, PL;

Janusz Rajski, West Linn, OR (US);

Lukasz Rybak, Poznan, PL;

Jedrzej Solecki, Poznan, PL;

Jerzy Tyszer, Poznan, PL;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3187 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3187 (2013.01); G01R 31/318547 (2013.01);
Abstract

Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.


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