The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Apr. 15, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chii-Ming Wu, Taipei, TW;

Ru-Shang Hsiao, Hsinchu County, TW;

Hung Pin Chen, Kaohsiung, TW;

Sen-Hong Syue, Hsinchu County, TW;

Chi-Cherng Jeng, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/045 (2013.01); H01L 29/66803 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method of fabricating a FinFET includes at last the following steps. A <551> direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the <551> direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.


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