The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Apr. 27, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Wei Sung, Kaohsiung, TW;

Yi-Hung Chen, Kaohsiung, TW;

Keng-Ying Liao, Tainan, TW;

Yi-Fang Yang, Tainan, TW;

Chih-Yu Wu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14609 (2013.01); H01L 27/14643 (2013.01); H01L 27/14687 (2013.01); H01L 27/14689 (2013.01);
Abstract

A semiconductor device and a method for fabricating thereof are provided. In the method for fabricating the semiconductor device, at first, a first semiconductor wafer including a first oxide layer and a second semiconductor wafer including a second oxide layer are provided. Next, the second oxide layer is bonded with the first oxide layer. Then, a through via is formed to through the second oxide layer and the first oxide layer, so as to form a sidewall cut on a sidewall of the through via at an interface of the first oxide layer and the second oxide layer. Then, an ashing operation is performed on the sidewall of the through via to form a protection layer on the sidewall of the through via. After the ashing operation is performed, a conductive material is deposited on the through via.


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