The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Oct. 28, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Yuki Mizutani, San Jose, CA (US);

Hiroyuki Ogawa, Yokkaichi, JP;

Fumiaki Toyama, Cupertino, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Fumitaka Amano, Yokkaichi, JP;

Kota Funayama, Yokkaichi, JP;

Akihiro Ueda, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 29/786 (2006.01); H01L 29/792 (2006.01); H01L 27/11568 (2017.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11568 (2013.01); H01L 29/0692 (2013.01); H01L 29/78642 (2013.01); H01L 29/7926 (2013.01);
Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.


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