The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Mar. 12, 2017
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian province, CN;

Inventors:

Li-Wei Feng, Kaohsiung, TW;

Ying-Chiao Wang, Changhua County, TW;

Yu-Chieh Lin, Kaohsiung, TW;

Chien-Ting Ho, Taichung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10855 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 27/10885 (2013.01);
Abstract

A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of storage node contact plugs. The semiconductor device includes a plurality of memory cells formed in the memory cell region. The isolation mesh includes a plurality of essentially homogeneous dielectric sidewalls and a plurality of first apertures defined by the dielectric sidewalls. The storage node contact plugs are respectively formed in the first apertures, and electrically connected to the memory cells respectively.


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