The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2018
Filed:
Nov. 15, 2004
Applicants:
Daewoong Suh, Phoenix, AZ (US);
Saikumar Jayaraman, Chandler, AZ (US);
Inventors:
Daewoong Suh, Phoenix, AZ (US);
Saikumar Jayaraman, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/4853 (2013.01); H01L 23/562 (2013.01); H05K 3/3436 (2013.01); H05K 3/3484 (2013.01); H01L 21/563 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15311 (2013.01); H05K 3/305 (2013.01); H05K 2201/10977 (2013.01); H05K 2203/043 (2013.01); H05K 2203/0568 (2013.01); Y02P 70/613 (2015.11);
Abstract
Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.