The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Dec. 16, 2015
Cypress Semiconductor Corporation, San Jose, CA (US);
Mark Ramsbey, Sunnyvale, CA (US);
Chun Chen, San Jose, CA (US);
Sameer Haddad, San Jose, CA (US);
Kuo Tung Chang, Saratoga, CA (US);
Unsoon Kim, San Jose, CA (US);
Shenqing Fang, Fremont, CA (US);
Yu Sun, Saratoga, CA (US);
Calvin Gabriel, Cupertino, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.