The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Feb. 12, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Feng Wei Kuo, Zhudong Township, TW;
Shuo-Mao Chen, New Taipei, TW;
Chin-Yuan Huang, Hsinchu, TW;
Kai-Yun Lin, Hsinchu, TW;
Ho-Hsiang Chen, Hsinchu, TW;
Chewn-Pu Jou, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate; and determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes performing an LVS check of the connecting substrate including the dummy layer; and adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check. The method further includes repeating the converting step, the determining step, and the performing the LVS check step based on the adjusted dummy layer location.