The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
Oct. 21, 2016
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Kam-Tou Sio, Hsinchu County, TW;
Ru-Gun Liu, Hsinchu County, TW;
Meng-Hung Shen, Hsin-Chu, TW;
Chun-Hung Liou, Hsinchu, TW;
Shu-Hui Sung, Hsinchu County, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsin-Chu, TW;
Abstract
A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.