The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Sep. 30, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chi-Hsi Wu, Hsinchu, TW;

Der-Chyang Yeh, Hsin-Chu, TW;

Hsien-Wei Chen, Hsinchu, TW;

Li-Hsien Huang, Hsinchu County, TW;

Kuan-Chung Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 22/14 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A semiconductor device including an integrated circuit, a plurality of conductive pillars, and a protection layer is provided. The integrated circuit includes a semiconductor substrate and an interconnection structure covering the semiconductor substrate, wherein the interconnection structure includes a plurality of patterned conductive layers and a plurality of inter-dielectric layers stacked alternately, the topmost patterned conductive layer of the patterned conductive layers is covered by the topmost inter-dielectric layer of the inter-dielectric layers, and the topmost patterned conductive layer is exposed by a plurality of openings of the topmost inter-dielectric layer. The conductive pillars are disposed on the topmost patterned conductive layer exposed by the openings, and the conductive pillars are electrically connected to the topmost patterned conductive layer through the openings. The protection layer covers the integrated circuit and the conductive pillars. A method for fabricating the semiconductor device and a method for fabricating integrated fan-out packages including the semiconductor device are also provided.


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Wu, Chi-Hsi. (2018). Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices (U.S. Patent No. 9911672). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9911672

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