The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Apr. 07, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

David F. Abdo, Tempe, AZ (US);

Sivanesan A/L Sathiapalan, Kuala Lumpur, MY;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/80 (2013.01); H01L 2224/0312 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/05547 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05601 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/80048 (2013.01); H01L 2224/80355 (2013.01); H01L 2224/80359 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/1033 (2013.01);
Abstract

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.


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