The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Mar. 18, 2016
Applicant:

Globalfoundries, Inc., Grand Cayman, KY;

Inventors:

Alban Zaka, Dresden, DE;

Ran Yan, Dresden, DE;

El Mehdi Bazizi, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 29/167 (2006.01); H01L 21/268 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/266 (2013.01); H01L 21/268 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/324 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 21/823807 (2013.01); H01L 27/0924 (2013.01); H01L 29/1041 (2013.01); H01L 29/167 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66492 (2013.01); H01L 21/26506 (2013.01);
Abstract

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.


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