The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Mar. 12, 2015
Applicants:

Sanken Electric Co., Ltd., Niiza-shi, Saitama, JP;

Shin-etsu Handotai Co. Ltd., Tokyo, JP;

Inventors:

Ken Sato, Miyoshi, JP;

Hiroshi Shikauchi, Niiza, JP;

Hirokazu Goto, Minato-ku, JP;

Masaru Shinomiya, Annaka, JP;

Kazunori Hagimoto, Takasaki, JP;

Keitaro Tsuchiya, Takasaki, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/207 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02378 (2013.01); H01L 21/02458 (2013.01); H01L 21/02579 (2013.01); H01L 29/2003 (2013.01); H01L 29/207 (2013.01); H01L 29/66462 (2013.01);
Abstract

A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region. As a result, it is possible to provide the semiconductor substrate which can reduce a leak current by enhancing crystallinity of the high-resistance layer while maintaining a high resistance of the high-resistance layer, and suppress occurrence of a decrease in electron mobility or current collapse in the channel layer by likewise enhancing crystallinity of the channel layer formed on the high-resistance layer.


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