The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2018

Filed:

Aug. 15, 2016
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Kun Liu, Singapore, SG;

Xiaoping Wang, Singapore, SG;

Francis Lionel Benistant, Singapore, SG;

Li Cao, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/76897 (2013.01); H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/41758 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01);
Abstract

Devices and methods for forming a device are disclosed. A transistor is formed on the substrate. The transistor includes a gate, a source and a drain. An insulation layer is formed on the substrate. The insulation layer is partially disposed on the gate and a sidewall of the gate. The drain is offset from the gate by the insulation layer. An overlayer is formed on the substrate covering the transistor and insulation layer. A field plate in the form of a field plate contact is formed in the overlayer. The field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.


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