The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2018

Filed:

Jul. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wan-Yu Lee, Taipei, TW;

Chun-Hao Tseng, Taichung, TW;

Jui Hsieh Lai, Taoyuan, TW;

Tien-Yu Huang, Shuishang Township, TW;

Ying-Hao Kuo, Hsinchu, TW;

Kuo-Chung Yee, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 23/31 (2006.01); H01L 31/0232 (2014.01); H01L 31/09 (2006.01); H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01); H01L 21/311 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/31111 (2013.01); H01L 21/481 (2013.01); H01L 21/4857 (2013.01); H01L 21/50 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 21/76838 (2013.01); H01L 23/293 (2013.01); H01L 23/3114 (2013.01); H01L 23/3171 (2013.01); H01L 23/48 (2013.01); H01L 23/538 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H01L 24/06 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/167 (2013.01); H01L 25/50 (2013.01); H01L 27/14618 (2013.01); H01L 31/0232 (2013.01); H01L 31/09 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/1032 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.


Find Patent Forward Citations

Loading…