The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
May. 16, 2016
Sandisk Technologies, Llc., Plano, TX (US);
Zhenyu Lu, Milpitas, CA (US);
Kota Funayama, Yokkaichi, JP;
Chun-Ming Wang, Fremont, CA (US);
Jixin Yu, Milpitas, CA (US);
Chenche Huang, Campbell, CA (US);
Tong Zhang, Palo Alto, CA (US);
Daxin Mao, Cupertino, CA (US);
Johann Alsmeier, San Jose, CA (US);
Makoto Yoshida, Yokkaichi, JP;
Lauren Matsumoto, Milpitas, CA (US);
SANDISK TECHNOLOGIES LLC, Plano, TX (US);
Abstract
A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.