The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2018
Filed:
Nov. 02, 2016
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Lanxiang Wang, Singapore, SG;
Hong Liao, Singapore, SG;
Chao Jiang, Singapore, SG;
Bo Liu, Singapore, SG;
Xin Xu, Singapore, SG;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/11521 (2017.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01); H01L 29/92 (2006.01); H01L 27/108 (2006.01); H01L 27/11502 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 29/42324 (2013.01); H01L 29/4966 (2013.01); H01L 23/5223 (2013.01); H01L 27/0805 (2013.01); H01L 27/10852 (2013.01); H01L 27/11502 (2013.01); H01L 29/92 (2013.01); H01L 2924/30105 (2013.01);
Abstract
A method for fabricating memory device includes the steps of: providing a substrate; forming a tunnel oxide layer on the substrate; forming a first gate layer on the tunnel oxide layer; forming a negative capacitance (NC) insulating layer on the first gate layer; and forming a second gate layer on the NC insulating layer. Preferably, the second gate layer further includes a work function metal layer on the NC insulating layer and a low resistance metal layer on the work function metal layer.