The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Mar. 29, 2017
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian province, CN;

Inventors:

Chia-Chen Wu, Nantou County, TW;

Pin-Hong Chen, Tainan, TW;

Kai-Jiun Chang, Taoyuan, TW;

Yi-An Huang, New Taipei, TW;

Chih-Chieh Tsai, Kaohsiung, TW;

Tzu-Chieh Chen, Pingtung County, TW;

Tsun-Min Cheng, Changhua County, TW;

Yi-Wei Chen, Taichung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/321 (2013.01); H01L 21/76889 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.


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